Comparison of two multi-bit vectors is a common operation performed in digital logic circuits. It is also common to perform a comparison operation for equality in the digital logic circuits. In addition, sometimes it is required to determine if two multi-bit vectors differ in value by a certain amount. For example, it is often required to perform a comparison operation to find whether the difference between two multi-bit vectors is equal to +1, +2, . . . or +n. Frequently, it is also required to determine if the difference between the two multi-bit vectors A[N−1:0] and B[N−1:0] is within a range of +m to +n, m<n, when both m and n are known, i.e., to evaluate inequality +m≦A[N−1:0]−B[N−1:0]≦+n.
Traditionally, the comparison operation performed on two multi-bit vectors to check for equality, such as A[N−1:0]==B[N−1:0]+n would require an N-bit adder/subtractor followed by an N-bit comparator in a digital logic circuit. Further, conventional techniques to perform an operation to determine whether the difference between two vectors is within a certain range require at least one adder/subtractor and multiple comparators. Generally, each adder/subtractor within a digital logic circuit requires considerable number of logic gates, which requires significant silicon area. In addition, it results in significant delay.